{
  "schema_version": "jgste-hardware-flows-v1",
  "observed_at": "2026-09-08T07:51:45.5126747Z",
  "system": {
    "cpu": "AMD Ryzen 5 3600X 6-Core Processor",
    "gpu": "NVIDIA GeForce RTX 2070",
    "board": "PRIME X570-P",
    "memory_bytes": 34359738368
  },
  "units": {
    "rate": "decimal bytes per second",
    "capacity": "binary KiB/MiB/GiB unless drive TB",
    "unknown": "null is unavailable, never zero"
  },
  "sources": [
    {
      "id": "amd",
      "title": "amd ryzen 5 3600x specifications",
      "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html",
      "location": "specifications"
    },
    {
      "id": "asus",
      "title": "asus prime x570-p user manual",
      "url": "https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X570-P/E17441_PRIME_X570-P_UM_v3_WEB.pdf",
      "location": "specification summary pp. viii–ix; motherboard layout"
    },
    {
      "id": "nvidia",
      "title": "nvidia geforce rtx 2070 specifications",
      "url": "https://www.nvidia.com/content/nvidiaGDC/gb/en_GB/geforce/graphics-cards/rtx-2070.html",
      "location": "full specifications: memory"
    },
    {
      "id": "turing",
      "title": "nvidia turing tuning guide",
      "url": "https://docs.nvidia.com/cuda/turing-tuning-guide/index.html",
      "location": "1.4.1.3 occupancy; 1.4.3.1 unified shared memory/l1"
    },
    {
      "id": "pcisig",
      "title": "pci-sig: pcie 3.0 encoding and rate",
      "url": "https://pcisig.com/how-does-pcie-30-8gts-double-pcie-20-5gts-bit-rate",
      "location": "8 GT/s and 128b/130b encoding"
    },
    {
      "id": "crucial",
      "title": "crucial p1 product flyer",
      "url": "https://content.crucial.com/content/dam/crucial/ssd-products/p1/flyer/crucial-p1-nvme-m2-ssd-productflyer.pdf",
      "location": "ct1000p1ssd8 1000 GB row"
    },
    {
      "id": "nvml",
      "title": "nvidia system management interface",
      "url": "https://docs.nvidia.com/deploy/nvidia-smi/index.html",
      "location": "pcie throughput; dmon; utilization"
    },
    {
      "id": "zen2",
      "title": "amd zen 2: hot chips 31",
      "url": "https://old.hotchips.org/hc31/HC31_1.1_AMD_ZEN2.pdf",
      "location": "slides 10, 12, 15: load/store ports, cache paths, memory bandwidth"
    },
    {
      "id": "wd",
      "title": "wd blue 3d nand sata ssd datasheet",
      "url": "https://documents.sandisk.com/content/dam/asset-library/en_us/assets/public/western-digital/product/internal-drives/wd-blue-ssd/data-sheet-wd-blue-3d-nand-sata-ssd-2879-800092.pdf",
      "location": "p. 2, 1 TB column; april 2019"
    },
    {
      "id": "turing-whitepaper",
      "title": "nvidia turing architecture whitepaper",
      "url": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf",
      "location": "appendix b, printed pp.62–64: rtx 2070 / tu106"
    }
  ],
  "nodes": [
    {
      "id": "cpu-exec",
      "label": "cpu execution",
      "capacity": "6 cores · 12 threads",
      "detail": "ryzen 5 3600x; arithmetic throughput is operations/s, not bytes/s",
      "group": "cpu"
    },
    {
      "id": "cpu-reg",
      "label": "cpu registers",
      "capacity": "per hardware thread",
      "detail": "architectural and physical registers differ; no register traffic counter connected",
      "group": "cpu"
    },
    {
      "id": "cpu-l1d",
      "label": "cpu l1 data",
      "capacity": "32 KiB / core · 192 KiB total",
      "detail": "six private caches; 64-byte lines; threads on a core share its cache",
      "group": "cpu"
    },
    {
      "id": "cpu-l1i",
      "label": "cpu l1 instruction",
      "capacity": "32 KiB / core · 192 KiB total",
      "detail": "six private instruction caches; instruction fetch is separate from data loads",
      "group": "cpu"
    },
    {
      "id": "cpu-l2",
      "label": "cpu l2",
      "capacity": "512 KiB / core · 3 MiB total",
      "detail": "six private unified caches; not a single shared 3 MiB pool",
      "group": "cpu"
    },
    {
      "id": "cpu-l3",
      "label": "cpu l3",
      "capacity": "2 × 16 MiB · 32 MiB total",
      "detail": "os-reported sharing groups: three active cores per group; cross-group traffic differs",
      "group": "cpu"
    },
    {
      "id": "fabric",
      "label": "cpu fabric + memory control",
      "capacity": "internal interconnect",
      "detail": "connects core complexes, memory controllers and io; clock and traffic not measured",
      "group": "cpu"
    },
    {
      "id": "ram",
      "label": "system ram",
      "capacity": "32 GiB · 2 × 16 GiB",
      "detail": "ddr4-3200 reported in a2/b2; two-channel 51.2 GB/s calculation is conditional on both channels active",
      "group": "memory"
    },
    {
      "id": "root",
      "label": "cpu pcie root",
      "capacity": "cpu io die",
      "detail": "cpu io root for separate gpu and nvme branches plus the x570 uplink; internal fabric traffic not measured",
      "group": "io"
    },
    {
      "id": "chipset",
      "label": "x570 chipset",
      "capacity": "shared io uplink",
      "detail": "sata, ethernet and some usb share its upstream branch; gpu now has a separate cpu-root path",
      "group": "io"
    },
    {
      "id": "gpu-pcie",
      "label": "gpu pcie endpoint",
      "capacity": "observed gen 3 ×16",
      "detail": "rtx 2070 in upper pciex16_1 slot; full ×16 width and direct cpu-root route verified after relocation",
      "group": "gpu"
    },
    {
      "id": "gpu-l2",
      "label": "gpu l2",
      "capacity": "4 MiB shared",
      "detail": "unified device cache; dma and kernel traffic need not all take identical routes",
      "group": "gpu"
    },
    {
      "id": "gpu-l1",
      "label": "gpu l1 + shared",
      "capacity": "96 KiB / sm, split 64/32",
      "detail": "l1/texture cache and software-managed shared memory share capacity, not identical paths",
      "group": "gpu"
    },
    {
      "id": "gpu-reg",
      "label": "gpu registers",
      "capacity": "256 KiB / sm",
      "detail": "64K 32-bit registers per streaming multiprocessor; workload-dependent allocation",
      "group": "gpu"
    },
    {
      "id": "gpu-exec",
      "label": "gpu execution",
      "capacity": "36 sm · 2304 cuda cores",
      "detail": "turing; compute busy % is not data bandwidth",
      "group": "gpu"
    },
    {
      "id": "vram",
      "label": "gpu vram",
      "capacity": "8 GiB gddr6",
      "detail": "14 Gbit/s per pin × 256 pins / 8 = 448 GB/s rated memory bandwidth",
      "group": "gpu"
    },
    {
      "id": "nvme",
      "label": "nvme ssd",
      "capacity": "1 TB · crucial p1",
      "detail": "ct1000p1ssd8; observed cpu branch and pcie gen 3 ×4",
      "group": "io"
    },
    {
      "id": "sata",
      "label": "sata ssd",
      "capacity": "1 TB · wd blue 3d",
      "detail": "wds100t2b0a-00sm50; x570 sata controller; sata 6 Gbit/s capability",
      "group": "io"
    },
    {
      "id": "net",
      "label": "ethernet",
      "capacity": "1 Gbit/s link reported",
      "detail": "realtek pcie gbe; negotiated wire rate, not internet capacity",
      "group": "io"
    },
    {
      "id": "usb",
      "label": "usb ports",
      "capacity": "up to 10 Gbit/s",
      "detail": "x570 and cpu supply different ports; no endpoint speed/port mapping or traffic connected",
      "group": "io"
    }
  ],
  "links": [
    {
      "id": "cpu-reg-exec",
      "from": "cpu-reg",
      "to": "cpu-exec",
      "label": "cpu register access",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. depends on instruction mix, operand width, dependency chains, ports and clocks; no single bytes/s value is established."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        }
      ]
    },
    {
      "id": "cpu-l1d-reg",
      "from": "cpu-l1d",
      "to": "cpu-reg",
      "label": "cpu data loads + stores",
      "directions": [
        {
          "id": "load",
          "label": "load · per core",
          "limit_bytes_per_second": 243200000000,
          "limit_label": "calculated · 64 B/cycle at assumed 3.8 GHz per core",
          "kind": "calculated",
          "source": "amd zen 2 slide 10; 2 × 32-byte loads/cycle; clock is a scenario, not measured",
          "live": null
        },
        {
          "id": "store",
          "label": "store · per core",
          "limit_bytes_per_second": 121600000000,
          "limit_label": "calculated · 32 B/cycle at assumed 3.8 GHz per core",
          "kind": "calculated",
          "source": "amd zen 2 slide 10; 1 × 32-byte store/cycle; clock is a scenario, not measured",
          "live": null,
          "from": "cpu-reg",
          "to": "cpu-l1d"
        }
      ],
      "notes": [
        "not measured. these are architectural throughput scenarios at 3.8 GHz, not rates observed on this pc.",
        "load + store port capacity can total 96 B/cycle under suitable parallel instructions; dependencies, alignment, access patterns and other work reduce it.",
        "per physical core; smt threads share the same resources. never multiply by 12 or call it ram bandwidth."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        },
        {
          "label": "amd zen 2: hot chips 31",
          "url": "https://old.hotchips.org/hc31/HC31_1.1_AMD_ZEN2.pdf"
        }
      ]
    },
    {
      "id": "cpu-l1i-exec",
      "from": "cpu-l1i",
      "to": "cpu-exec",
      "label": "cpu instruction fetch",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. bytes fetched differ from instructions decoded and operations executed."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        }
      ]
    },
    {
      "id": "cpu-l2-l1d",
      "from": "cpu-l2",
      "to": "cpu-l1d",
      "label": "cpu l2 ↔ l1 data",
      "directions": [
        {
          "id": "path",
          "label": "data-cache path · per core",
          "limit_bytes_per_second": 121600000000,
          "limit_label": "calculated · 32 B/cycle at assumed 3.8 GHz per core",
          "kind": "calculated",
          "source": "amd zen 2 slide 12; path width × illustrative clock; not an observed rate",
          "live": null
        }
      ],
      "notes": [
        "not measured. fills and evictions occur in cache lines, while program operands may be smaller.",
        "amd labels this path 32 B/cycle. 121.6 GB/s assumes 3.8 GHz; no sustained rate or concurrent fill/eviction sum is asserted."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        },
        {
          "label": "amd zen 2: hot chips 31",
          "url": "https://old.hotchips.org/hc31/HC31_1.1_AMD_ZEN2.pdf"
        }
      ]
    },
    {
      "id": "cpu-l2-l1i",
      "from": "cpu-l2",
      "to": "cpu-l1i",
      "label": "cpu l2 → l1 instruction",
      "directions": [
        {
          "id": "path",
          "label": "instruction refill · per core",
          "limit_bytes_per_second": 121600000000,
          "limit_label": "calculated · 32 B/cycle at assumed 3.8 GHz per core",
          "kind": "calculated",
          "source": "amd zen 2 slide 12; path width × illustrative clock; not an observed rate",
          "live": null
        }
      ],
      "notes": [
        "not measured. instruction refill path shown separately from data-cache writes.",
        "amd labels this path 32 B/cycle. 121.6 GB/s assumes 3.8 GHz; no sustained rate or concurrent fill/eviction sum is asserted."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        },
        {
          "label": "amd zen 2: hot chips 31",
          "url": "https://old.hotchips.org/hc31/HC31_1.1_AMD_ZEN2.pdf"
        }
      ]
    },
    {
      "id": "cpu-l3-l2",
      "from": "cpu-l3",
      "to": "cpu-l2",
      "label": "cpu l3 ↔ l2",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. cache hierarchy is a logical access/refill map, not a compulsory trip through each cache for every byte."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        }
      ]
    },
    {
      "id": "fabric-l3",
      "from": "fabric",
      "to": "cpu-l3",
      "label": "cpu core complex ↔ fabric",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. inter-core coherence, misses and prefetches can produce different traffic from application reads."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        }
      ]
    },
    {
      "id": "ram-fabric",
      "from": "ram",
      "to": "fabric",
      "label": "ram ↔ memory controller",
      "directions": [
        {
          "id": "shared",
          "label": "read + write share this bus",
          "limit_bytes_per_second": 51200000000,
          "limit_label": "calculated · 2 active channels at 3200 MT/s",
          "kind": "calculated",
          "source": "windows module configuration + amd two-channel specification; 3200e6 × 8 bytes × 2",
          "live": null
        }
      ],
      "notes": [
        "not measured. a2/b2 population supports the two-channel scenario but does not directly prove controller mode.",
        "51.2 GB/s is the combined data-pin ceiling, shared by reads and writes; do not assign it independently to each direction.",
        "refresh, turnaround, command overhead and access patterns reduce sustained throughput."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        },
        {
          "label": "asus prime x570-p user manual",
          "url": "https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X570-P/E17441_PRIME_X570-P_UM_v3_WEB.pdf"
        }
      ]
    },
    {
      "id": "root-fabric",
      "from": "root",
      "to": "fabric",
      "label": "cpu io ↔ memory fabric",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. internal io traffic includes dma and coherence; do not sum external device counters as a fabric measurement."
      ],
      "source_urls": [
        {
          "label": "amd ryzen 5 3600x specifications",
          "url": "https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-3000-series/amd-ryzen-5-3600x.html"
        }
      ]
    },
    {
      "id": "chipset-root",
      "from": "chipset",
      "to": "root",
      "label": "x570 ↔ cpu uplink",
      "directions": [
        {
          "id": "up",
          "label": "chipset → cpu",
          "limit_bytes_per_second": 7876923076.923077,
          "limit_label": "calculated scenario · if pcie 4.0 ×4",
          "kind": "calculated",
          "source": "conditional link formula only: 16e9 × 128/130 × 4 / 8; installed uplink not verified",
          "live": null
        },
        {
          "id": "down",
          "label": "cpu → chipset",
          "limit_bytes_per_second": 7876923076.923077,
          "limit_label": "calculated scenario · if pcie 4.0 ×4",
          "kind": "calculated",
          "source": "conditional link formula only: 16e9 × 128/130 × 4 / 8; installed uplink not verified",
          "live": null,
          "from": "root",
          "to": "chipset"
        }
      ],
      "notes": [
        "not measured. 7.877 GB/s is a gen 4 ×4 scenario, not a verified installed limit; current uplink generation and width were not established.",
        "sata, ethernet and some usb traffic compete on the chipset uplink. the gpu and cpu-attached nvme use separate root branches."
      ],
      "source_urls": [
        {
          "label": "asus prime x570-p user manual",
          "url": "https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X570-P/E17441_PRIME_X570-P_UM_v3_WEB.pdf"
        },
        {
          "label": "pci-sig: pcie 3.0 encoding and rate",
          "url": "https://pcisig.com/how-does-pcie-30-8gts-double-pcie-20-5gts-bit-rate"
        }
      ]
    },
    {
      "id": "gpu-host",
      "from": "root",
      "to": "gpu-pcie",
      "label": "gpu ↔ host pcie",
      "directions": [
        {
          "id": "host-to-gpu",
          "label": "host → gpu",
          "limit_bytes_per_second": 15753846153.846153,
          "limit_label": "calculated · observed gen 3 ×16",
          "kind": "calculated",
          "source": "nvidia-smi current link; 8e9 × 128/130 × 16 / 8; before packet overhead",
          "live": {
            "collection": "gpus",
            "match": {
              "field": "model",
              "value": "NVIDIA GeForce RTX 2070"
            },
            "field": "pcie_receive_mb_per_second",
            "scale": 1000000
          }
        },
        {
          "id": "gpu-to-host",
          "label": "gpu → host",
          "limit_bytes_per_second": 15753846153.846153,
          "limit_label": "calculated · observed gen 3 ×16",
          "kind": "calculated",
          "source": "nvidia-smi current link; 8e9 × 128/130 × 16 / 8; before packet overhead",
          "live": {
            "collection": "gpus",
            "match": {
              "field": "model",
              "value": "NVIDIA GeForce RTX 2070"
            },
            "field": "pcie_send_mb_per_second",
            "scale": 1000000
          },
          "from": "gpu-pcie",
          "to": "root"
        }
      ],
      "notes": [
        "link traffic is coarse nvidia-smi reporting; zero may hide small transfers. its internal sampling interval differs from the windows sample.",
        "after the card was moved from the lower to the upper long slot, both nvidia and windows report ×16. the device path now goes directly to the cpu root.",
        "the earlier ×4 link had a 3.938 GB/s coding ceiling per direction; the current ×16 link has 15.754 GB/s. this fourfold ceiling change is not a measured application speedup.",
        "windows pcie property reports gen 1 while nvidia-smi reports gen 3; cached or power-state-dependent generation readings differ. both agree on ×16 width.",
        "the pre-move inventory and one-minute csv remain historical ×4 records. the current catalog is dated after relocation."
      ],
      "source_urls": [
        {
          "label": "pci-sig: pcie 3.0 encoding and rate",
          "url": "https://pcisig.com/how-does-pcie-30-8gts-double-pcie-20-5gts-bit-rate"
        },
        {
          "label": "nvidia system management interface",
          "url": "https://docs.nvidia.com/deploy/nvidia-smi/index.html"
        },
        {
          "label": "asus prime x570-p user manual",
          "url": "https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X570-P/E17441_PRIME_X570-P_UM_v3_WEB.pdf"
        }
      ]
    },
    {
      "id": "gpu-dma",
      "from": "gpu-pcie",
      "to": "gpu-l2",
      "label": "gpu dma + device memory",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not separately measured. this is a logical connection; the host-link counter does not measure internal l2 or vram traffic."
      ],
      "source_urls": [
        {
          "label": "nvidia turing tuning guide",
          "url": "https://docs.nvidia.com/cuda/turing-tuning-guide/index.html"
        },
        {
          "label": "nvidia system management interface",
          "url": "https://docs.nvidia.com/deploy/nvidia-smi/index.html"
        }
      ]
    },
    {
      "id": "gpu-l2-vram",
      "from": "vram",
      "to": "gpu-l2",
      "label": "gpu vram ↔ memory controller",
      "directions": [
        {
          "id": "shared",
          "label": "read + write share memory pins",
          "limit_bytes_per_second": 448000000000,
          "limit_label": "documented · rated memory bandwidth",
          "kind": "documented",
          "source": "nvidia rtx 2070 specification: 14e9 × 256 / 8",
          "live": null
        }
      ],
      "notes": [
        "not measured. rated 448 GB/s is local gddr6 bandwidth, not the host pcie link or l2 hit bandwidth.",
        "current power state, memory clock, access pattern and contention affect actual rate. gpu memory-active % is not a byte count."
      ],
      "source_urls": [
        {
          "label": "nvidia geforce rtx 2070 specifications",
          "url": "https://www.nvidia.com/content/nvidiaGDC/gb/en_GB/geforce/graphics-cards/rtx-2070.html"
        },
        {
          "label": "nvidia turing tuning guide",
          "url": "https://docs.nvidia.com/cuda/turing-tuning-guide/index.html"
        },
        {
          "label": "nvidia system management interface",
          "url": "https://docs.nvidia.com/deploy/nvidia-smi/index.html"
        }
      ]
    },
    {
      "id": "gpu-l1-l2",
      "from": "gpu-l2",
      "to": "gpu-l1",
      "label": "gpu l2 ↔ l1 cache",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. this edge describes global-memory cache traffic; shared-memory accesses are local to each sm and do not imply an l2 transfer."
      ],
      "source_urls": [
        {
          "label": "nvidia turing tuning guide",
          "url": "https://docs.nvidia.com/cuda/turing-tuning-guide/index.html"
        },
        {
          "label": "nvidia turing architecture whitepaper, appendix b",
          "url": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf"
        }
      ]
    },
    {
      "id": "gpu-reg-l1",
      "from": "gpu-l1",
      "to": "gpu-reg",
      "label": "gpu local loads + stores",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. per-sm l1/texture caching and shared-memory bank accesses are distinct paths grouped for visibility; no universal combined bandwidth assigned."
      ],
      "source_urls": [
        {
          "label": "nvidia turing tuning guide",
          "url": "https://docs.nvidia.com/cuda/turing-tuning-guide/index.html"
        }
      ]
    },
    {
      "id": "gpu-reg-exec",
      "from": "gpu-reg",
      "to": "gpu-exec",
      "label": "gpu register access",
      "directions": [
        {
          "id": "both",
          "label": "data path",
          "limit_bytes_per_second": null,
          "limit_label": "no verified fixed rate",
          "kind": "unknown",
          "source": "no throughput counter connected",
          "live": null
        }
      ],
      "notes": [
        "not measured. register access, instruction issue and floating-point operation rates are different quantities."
      ],
      "source_urls": [
        {
          "label": "nvidia turing tuning guide",
          "url": "https://docs.nvidia.com/cuda/turing-tuning-guide/index.html"
        }
      ]
    },
    {
      "id": "nvme-root",
      "from": "nvme",
      "to": "root",
      "label": "nvme ssd ↔ cpu",
      "directions": [
        {
          "id": "read",
          "label": "ssd → host",
          "limit_bytes_per_second": 2000000000,
          "limit_label": "documented · typical sequential read",
          "kind": "documented",
          "source": "crucial p1 1 TB product flyer",
          "live": {
            "collection": "disks",
            "match": {
              "field": "model",
              "value": "CT1000P1SSD8"
            },
            "field": "read_bytes_per_second",
            "scale": 1
          }
        },
        {
          "id": "write",
          "label": "host → ssd",
          "limit_bytes_per_second": 1700000000,
          "limit_label": "documented · typical sequential write",
          "kind": "documented",
          "source": "crucial p1 1 TB product flyer",
          "live": {
            "collection": "disks",
            "match": {
              "field": "model",
              "value": "CT1000P1SSD8"
            },
            "field": "write_bytes_per_second",
            "scale": 1
          },
          "from": "root",
          "to": "nvme"
        }
      ],
      "notes": [
        "observed pcie gen 3 ×4 has a separate 3.938 GB/s link ceiling each direction.",
        "2.0/1.7 GB/s are vendor typical drive results, not guaranteed or measured maxima. write cache exhaustion can lower sustained write speed.",
        "windows physical-disk bytes/s measures host io. it is not nand bus traffic; random io, queue depth and caching change results."
      ],
      "source_urls": [
        {
          "label": "crucial p1 product flyer",
          "url": "https://content.crucial.com/content/dam/crucial/ssd-products/p1/flyer/crucial-p1-nvme-m2-ssd-productflyer.pdf"
        },
        {
          "label": "pci-sig: pcie 3.0 encoding and rate",
          "url": "https://pcisig.com/how-does-pcie-30-8gts-double-pcie-20-5gts-bit-rate"
        }
      ]
    },
    {
      "id": "sata-chipset",
      "from": "sata",
      "to": "chipset",
      "label": "sata ssd ↔ chipset",
      "directions": [
        {
          "id": "read",
          "label": "ssd → host",
          "limit_bytes_per_second": 560000000,
          "limit_label": "documented · up to 560 MB/s sequential read",
          "kind": "documented",
          "source": "wd blue 3d nand sata ssd datasheet, 1 TB column",
          "live": {
            "collection": "disks",
            "match": {
              "field": "model",
              "value": "WDC  WDS100T2B0A-00SM50"
            },
            "field": "read_bytes_per_second",
            "scale": 1
          }
        },
        {
          "id": "write",
          "label": "host → ssd",
          "limit_bytes_per_second": 530000000,
          "limit_label": "documented · up to 530 MB/s sequential write",
          "kind": "documented",
          "source": "wd blue 3d nand sata ssd datasheet, 1 TB column",
          "live": {
            "collection": "disks",
            "match": {
              "field": "model",
              "value": "WDC  WDS100T2B0A-00SM50"
            },
            "field": "write_bytes_per_second",
            "scale": 1
          },
          "from": "chipset",
          "to": "sata"
        }
      ],
      "notes": [
        "vendor drive ratings are 560 MB/s read and 530 MB/s write; neither is a measured sustained result. the separate sata 6 Gbit/s encoding ceiling is 600 MB/s.",
        "current sata negotiation not directly read; 600 MB/s is the interface capability, not a drive benchmark or simultaneous read/write promise.",
        "windows rates are host io from physical-disk counters, not physical flash writes."
      ],
      "source_urls": [
        {
          "label": "asus prime x570-p user manual",
          "url": "https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X570-P/E17441_PRIME_X570-P_UM_v3_WEB.pdf"
        },
        {
          "label": "wd blue 3d nand sata ssd datasheet",
          "url": "https://documents.sandisk.com/content/dam/asset-library/en_us/assets/public/western-digital/product/internal-drives/wd-blue-ssd/data-sheet-wd-blue-3d-nand-sata-ssd-2879-800092.pdf"
        }
      ]
    },
    {
      "id": "net-chipset",
      "duplex_capture": {"full":true,"link_bits_per_second":1000000000,"observed_on":"2026-09-08","source":"windows MSFT_NetAdapter.FullDuplex"},
      "from": "net",
      "to": "chipset",
      "label": "ethernet ↔ host",
      "directions": [
        {
          "id": "receive",
          "label": "network → host",
          "limit_bytes_per_second": 125000000,
          "limit_label": "calculated · 1 Gbit/s negotiated link",
          "kind": "calculated",
          "source": "windows link speed / 8",
          "live": {
            "collection": "network",
            "match": {
              "field": "model",
              "value": "Realtek PCIe GbE Family Controller"
            },
            "field": "receive_bytes_per_second",
            "scale": 1
          }
        },
        {
          "id": "send",
          "label": "host → network",
          "limit_bytes_per_second": 125000000,
          "limit_label": "calculated · 1 Gbit/s negotiated link",
          "kind": "calculated",
          "source": "windows link speed / 8",
          "live": {
            "collection": "network",
            "match": {
              "field": "model",
              "value": "Realtek PCIe GbE Family Controller"
            },
            "field": "send_bytes_per_second",
            "scale": 1
          },
          "from": "chipset",
          "to": "net"
        }
      ],
      "notes": [
        "the nic reports pcie gen 1 ×1: calculated 250 MB/s per direction after 8b/10b encoding, before packets. the 125 MB/s displayed limit is its slower external 1 Gbit/s ethernet wire.",
        "link speed is not internet capacity or application payload speed; headers and framing consume bytes. full duplex was read from windows on 2026-09-08; duplex is a dated capture, not a live feed field."
      ],
      "source_urls": [
        {
          "label": "asus prime x570-p user manual",
          "url": "https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X570-P/E17441_PRIME_X570-P_UM_v3_WEB.pdf"
        }
      ]
    },
    {
      "id": "usb-chipset",
      "from": "usb",
      "to": "chipset",
      "label": "usb ports ↔ host",
      "directions": [
        {
          "id": "port",
          "label": "per gen 2 port",
          "limit_bytes_per_second": 1250000000,
          "limit_label": "calculated · 10 Gbit/s raw signaling / 8",
          "kind": "calculated",
          "source": "asus x570 gen 2 ports; raw line-rate equivalent",
          "live": null
        }
      ],
      "notes": [
        "not measured. 1.25 GB/s is a raw rate equivalent before encoding and protocol overhead; not usable payload.",
        "the board also has cpu usb ports, 5 Gbit/s ports and usb 2.0 ports; the line is representative, not a mapping of every plug.",
        "connected device generation, negotiated mode, hubs and actual port routing are not inventoried."
      ],
      "source_urls": [
        {
          "label": "asus prime x570-p user manual",
          "url": "https://dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/PRIME_X570-P/E17441_PRIME_X570-P_UM_v3_WEB.pdf"
        }
      ]
    }
  ]
}